
\subsection{APB Advanced Timer Registers}
{\small
\begin{tabularx}{\textwidth}{|l|l|l|l|l|l|X|}
  \hline
  \textbf{Name} & \textbf{Address}  & \textbf{Size} & \textbf{Type} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
  \hline
  T0\_CMD & \texttt{0x1A104000} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER0 command register.\\
  \hline
  T0\_CONFIG & \texttt{0x1A104004} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER0 configuration register.\\
  \hline
  T0\_THRESHOLD & \texttt{0x1A104008} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER0 threshold configuration register.\\
  \hline
  T0\_TH\_CHANNEL0 & \texttt{0x1A10400C} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER0 channel 0 threshold configuration register.\\
  \hline
  T0\_TH\_CHANNEL1 & \texttt{0x1A104010} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER0 channel 1 threshold configuration register.\\
  \hline
  T0\_TH\_CHANNEL2 & \texttt{0x1A104014} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER0 channel 2 threshold configuration register.\\
  \hline
  T0\_TH\_CHANNEL3 & \texttt{0x1A104018} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER0 channel 3 threshold configuration register.\\
  \hline
  T0\_COUNTER & \texttt{0x1A10402C} & 32 & Status & R & \texttt{0x00000000} & ADV\_TIMER0 counter register.\\
  \hline
  T1\_CMD & \texttt{0x1A104040} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER1 command register.\\
  \hline
  T1\_CONFIG & \texttt{0x1A104044} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER1 configuration register.\\
  \hline
  T1\_THRESHOLD & \texttt{0x1A104048} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER1 threshold configuration register.\\
  \hline
  T1\_TH\_CHANNEL0 & \texttt{0x1A10404C} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER1 channel 0 threshold configuration register.\\
  \hline
  T1\_TH\_CHANNEL1 & \texttt{0x1A104050} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER1 channel 1 threshold configuration register.\\
  \hline
  T1\_TH\_CHANNEL2 & \texttt{0x1A104054} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER1 channel 2 threshold configuration register.\\
  \hline
  T1\_TH\_CHANNEL3 & \texttt{0x1A104058} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER1 channel 3 threshold configuration register.\\
  \hline
  T1\_COUNTER & \texttt{0x1A10406C} & 32 & Status & R & \texttt{0x00000000} & ADV\_TIMER1 counter register.\\
  \hline
  T2\_CMD & \texttt{0x1A104080} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER2 command register.\\
  \hline
  T2\_CONFIG & \texttt{0x1A104084} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER2 configuration register.\\
  \hline
  T2\_THRESHOLD & \texttt{0x1A104088} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER2 threshold configuration register.\\
  \hline
  T2\_TH\_CHANNEL0 & \texttt{0x1A10408C} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER2 channel 0 threshold configuration register.\\
  \hline
  T2\_TH\_CHANNEL1 & \texttt{0x1A104090} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER2 channel 1 threshold configuration register.\\
  \hline
  T2\_TH\_CHANNEL2 & \texttt{0x1A104094} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER2 channel 2 threshold configuration register.\\
  \hline
  T2\_TH\_CHANNEL3 & \texttt{0x1A104098} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER2 channel 3 threshold configuration register.\\
  \hline
  T2\_COUNTER & \texttt{0x1A1040AC} & 32 & Status & R & \texttt{0x00000000} & ADV\_TIMER2 counter register.\\
  \hline
  T3\_CMD & \texttt{0x1A1040C0} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER3 command register.\\
  \hline
  T3\_CONFIG & \texttt{0x1A1040C4} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER3 configuration register.\\
  \hline
  T3\_THRESHOLD & \texttt{0x1A1040C8} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER3 threshold configuration register.\\
  \hline
  T3\_TH\_CHANNEL0 & \texttt{0x1A1040CC} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER3 channel 0 threshold configuration register.\\
  \hline
  T3\_TH\_CHANNEL1 & \texttt{0x1A1040D0} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER3 channel 1 threshold configuration register.\\
  \hline
  T3\_TH\_CHANNEL2 & \texttt{0x1A1040D4} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER3 channel 2 threshold configuration register.\\
  \hline
  T3\_TH\_CHANNEL3 & \texttt{0x1A1040D8} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMER3 channel 3 threshold configuration register.\\
  \hline
  T3\_COUNTER & \texttt{0x1A1040EC} & 32 & Status & R & \texttt{0x00000000} & ADV\_TIMER3 counter register.\\
  \hline
  EVENT\_CFG & \texttt{0x1A104100} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMERS events configuration register.\\
  \hline
  CG & \texttt{0x1A104104} & 32 & Config & R/W & \texttt{0x00000000} & ADV\_TIMERS channels clock gating configuration register.\\
  \hline
  \caption{APB Advanced Timer}
\end{tabularx}
}


\regdoc{0x1A104000}{0x00000000}{T0\_CMD}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{11}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\tiny ARM} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~RESET~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~UPDATE~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~STOP~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~START~}}
  \end{bytefield}
}{
  \regitem{Bit 4}{ARM}{R/W}{ADV\_TIMER0 arm command bitfield.}
  \regitem{Bit 3}{RESET}{R/W}{ADV\_TIMER0 reset command bitfield.}
  \regitem{Bit 2}{UPDATE}{R/W}{ADV\_TIMER0 update command bitfield.}
  \regitem{Bit 1}{STOP}{R/W}{ADV\_TIMER0 stop command bitfield.}
  \regitem{Bit 0}{START}{R/W}{ADV\_TIMER0 start command bitfield.}
}


\regdoc{0x1A104004}{0x00000000}{T0\_CONFIG}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{8}{\color{lightgray}\rule{\width}{\height}} \bitbox{8}{PRESC} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{3}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~UPDOWNSEL~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~CLKSEL~}} \bitbox{3}{MODE} \bitbox{8}{INSEL}
  \end{bytefield}
}{
  \regitem{Bit 23 - 16}{PRESC}{R/W}{ADV\_TIMER0 prescaler value configuration bitfield.}
  \regitem{Bit 12}{UPDOWNSEL}{R/W}{ADV\_TIMER0 center-aligned mode configuration bitfield:\\- 1'b0: The counter counts up and down alternatively.\\- 1'b1: The counter counts up and resets to 0 when reach threshold.}
  \regitem{Bit 11}{CLKSEL}{R/W}{ADV\_TIMER0 clock source configuration bitfield:\\- 1'b0: FLL\\- 1'b1: reference clock at 32kHz}
  \regitem{Bit 10 - 8}{MODE}{R/W}{ADV\_TIMER0 trigger mode configuration bitfield:\\- 3'h0: trigger event at each clock cycle.\\- 3'h1: trigger event if input source is 0\\- 3'h2: trigger event if input source is 1\\- 3'h3: trigger event on input source rising edge\\- 3'h4: trigger event on input source falling edge\\- 3'h5: trigger event on input source falling or rising edge\\- 3'h6: trigger event on input source rising edge when armed\\- 3'h7: trigger event on input source falling edge when armed}
  \regitem{Bit 7 - 0}{INSEL}{R/W}{ADV\_TIMER0 input source configuration bitfield:\\- 0-31: GPIO[0] to GPIO[31]\\- 32-35: Channel 0 to 3 of ADV\_TIMER0\\- 36-39: Channel 0 to 3 of ADV\_TIMER1\\- 40-43: Channel 0 to 3 of ADV\_TIMER2\\- 44-47: Channel 0 to 3 of ADV\_TIMER3}
}


\regdoc{0x1A104008}{0x00000000}{T0\_THRESHOLD}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{TH\_HI} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH\_LO}
  \end{bytefield}
}{
  \regitem{Bit 31 - 16}{TH\_HI}{R/W}{ADV\_TIMER0 threshold high part configuration bitfield. It defines end counter value.}
  \regitem{Bit 15 - 0}{TH\_LO}{R/W}{ADV\_TIMER0 threshold low part configuration bitfield. It defines start counter value.}
}


\regdoc{0x1A10400C}{0x00000000}{T0\_TH\_CHANNEL0}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER0 channel 0 threshold configuration bitfield.}
}


\regdoc{0x1A104010}{0x00000000}{T0\_TH\_CHANNEL1}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER0 channel 1 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER0 channel 1 threshold configuration bitfield.}
}


\regdoc{0x1A104014}{0x00000000}{T0\_TH\_CHANNEL2}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER0 channel 2 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER0 channel 2 threshold configuration bitfield.}
}


\regdoc{0x1A104018}{0x00000000}{T0\_TH\_CHANNEL3}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER0 channel 3 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER0 channel 3 threshold configuration bitfield.}
}


\regdoc{0x1A104040}{0x00000000}{T1\_CMD}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{11}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\tiny ARM} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~RESET~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~UPDATE~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~STOP~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~START~}}
  \end{bytefield}
}{
  \regitem{Bit 4}{ARM}{R/W}{ADV\_TIMER1 arm command bitfield.}
  \regitem{Bit 3}{RESET}{R/W}{ADV\_TIMER1 reset command bitfield.}
  \regitem{Bit 2}{UPDATE}{R/W}{ADV\_TIMER1 update command bitfield.}
  \regitem{Bit 1}{STOP}{R/W}{ADV\_TIMER1 stop command bitfield.}
  \regitem{Bit 0}{START}{R/W}{ADV\_TIMER1 start command bitfield.}
}


\regdoc{0x1A104044}{0x00000000}{T1\_CONFIG}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{8}{\color{lightgray}\rule{\width}{\height}} \bitbox{8}{PRESC} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{3}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~UPDOWNSEL~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~CLKSEL~}} \bitbox{3}{MODE} \bitbox{8}{INSEL}
  \end{bytefield}
}{
  \regitem{Bit 23 - 16}{PRESC}{R/W}{ADV\_TIMER1 prescaler value configuration bitfield.}
  \regitem{Bit 12}{UPDOWNSEL}{R/W}{ADV\_TIMER1 center-aligned mode configuration bitfield:\\- 1'b0: The counter counts up and down alternatively.\\- 1'b1: The counter counts up and resets to 0 when reach threshold.}
  \regitem{Bit 11}{CLKSEL}{R/W}{ADV\_TIMER1 clock source configuration bitfield:\\- 1'b0: FLL\\- 1'b1: reference clock at 32kHz}
  \regitem{Bit 10 - 8}{MODE}{R/W}{ADV\_TIMER1 trigger mode configuration bitfield:\\- 3'h0: trigger event at each clock cycle.\\- 3'h1: trigger event if input source is 0\\- 3'h2: trigger event if input source is 1\\- 3'h3: trigger event on input source rising edge\\- 3'h4: trigger event on input source falling edge\\- 3'h5: trigger event on input source falling or rising edge\\- 3'h6: trigger event on input source rising edge when armed\\- 3'h7: trigger event on input source falling edge when armed}
  \regitem{Bit 7 - 0}{INSEL}{R/W}{ADV\_TIMER1 input source configuration bitfield:\\- 0-31: GPIO[0] to GPIO[31]\\- 32-35: Channel 0 to 3 of ADV\_TIMER0\\- 36-39: Channel 0 to 3 of ADV\_TIMER1\\- 40-43: Channel 0 to 3 of ADV\_TIMER2\\- 44-47: Channel 0 to 3 of ADV\_TIMER3}
}


\regdoc{0x1A104048}{0x00000000}{T1\_THRESHOLD}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{TH\_HI} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH\_LO}
  \end{bytefield}
}{
  \regitem{Bit 31 - 16}{TH\_HI}{R/W}{ADV\_TIMER1 threshold high part configuration bitfield. It defines end counter value.}
  \regitem{Bit 15 - 0}{TH\_LO}{R/W}{ADV\_TIMER1 threshold low part configuration bitfield. It defines start counter value.}
}


\regdoc{0x1A10404C}{0x00000000}{T1\_TH\_CHANNEL0}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER1 channel 0 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER1 channel 0 threshold configuration bitfield.}
}


\regdoc{0x1A104050}{0x00000000}{T1\_TH\_CHANNEL1}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER1 channel 1 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER1 channel 1 threshold configuration bitfield.}
}


\regdoc{0x1A104054}{0x00000000}{T1\_TH\_CHANNEL2}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER1 channel 2 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER1 channel 2 threshold configuration bitfield.}
}


\regdoc{0x1A104058}{0x00000000}{T1\_TH\_CHANNEL3}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER1 channel 3 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER1 channel 3 threshold configuration bitfield.}
}


\regdoc{0x1A104080}{0x00000000}{T2\_CMD}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{11}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\tiny ARM} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~RESET~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~UPDATE~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~STOP~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~START~}}
  \end{bytefield}
}{
  \regitem{Bit 4}{ARM}{R/W}{ADV\_TIMER2 arm command bitfield.}
  \regitem{Bit 3}{RESET}{R/W}{ADV\_TIMER2 reset command bitfield.}
  \regitem{Bit 2}{UPDATE}{R/W}{ADV\_TIMER2 update command bitfield.}
  \regitem{Bit 1}{STOP}{R/W}{ADV\_TIMER2 stop command bitfield.}
  \regitem{Bit 0}{START}{R/W}{ADV\_TIMER2 start command bitfield.}
}


\regdoc{0x1A104084}{0x00000000}{T2\_CONFIG}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{8}{\color{lightgray}\rule{\width}{\height}} \bitbox{8}{PRESC} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{3}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~UPDOWNSEL~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~CLKSEL~}} \bitbox{3}{MODE} \bitbox{8}{INSEL}
  \end{bytefield}
}{
  \regitem{Bit 23 - 16}{PRESC}{R/W}{ADV\_TIMER2 prescaler value configuration bitfield.}
  \regitem{Bit 12}{UPDOWNSEL}{R/W}{ADV\_TIMER2 center-aligned mode configuration bitfield:\\- 1'b0: The counter counts up and down alternatively.\\- 1'b1: The counter counts up and resets to 0 when reach threshold.}
  \regitem{Bit 11}{CLKSEL}{R/W}{ADV\_TIMER2 clock source configuration bitfield:\\- 1'b0: FLL\\- 1'b1: reference clock at 32kHz}
  \regitem{Bit 10 - 8}{MODE}{R/W}{ADV\_TIMER2 trigger mode configuration bitfield:\\- 3'h0: trigger event at each clock cycle.\\- 3'h1: trigger event if input source is 0\\- 3'h2: trigger event if input source is 1\\- 3'h3: trigger event on input source rising edge\\- 3'h4: trigger event on input source falling edge\\- 3'h5: trigger event on input source falling or rising edge\\- 3'h6: trigger event on input source rising edge when armed\\- 3'h7: trigger event on input source falling edge when armed}
  \regitem{Bit 7 - 0}{INSEL}{R/W}{ADV\_TIMER2 input source configuration bitfield:\\- 0-31: GPIO[0] to GPIO[31]\\- 32-35: Channel 0 to 3 of ADV\_TIMER0\\- 36-39: Channel 0 to 3 of ADV\_TIMER1\\- 40-43: Channel 0 to 3 of ADV\_TIMER2\\- 44-47: Channel 0 to 3 of ADV\_TIMER3}
}


\regdoc{0x1A104088}{0x00000000}{T2\_THRESHOLD}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{TH\_HI} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH\_LO}
  \end{bytefield}
}{
  \regitem{Bit 31 - 16}{TH\_HI}{R/W}{ADV\_TIMER2 threshold high part configuration bitfield. It defines end counter value.}
  \regitem{Bit 15 - 0}{TH\_LO}{R/W}{ADV\_TIMER2 threshold low part configuration bitfield. It defines start counter value.}
}


\regdoc{0x1A10408C}{0x00000000}{T2\_TH\_CHANNEL0}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER2 channel 0 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER2 channel 0 threshold configuration bitfield.}
}


\regdoc{0x1A104090}{0x00000000}{T2\_TH\_CHANNEL1}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER2 channel 1 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER2 channel 1 threshold configuration bitfield.}
}


\regdoc{0x1A104094}{0x00000000}{T2\_TH\_CHANNEL2}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER2 channel 2 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER2 channel 2 threshold configuration bitfield.}
}


\regdoc{0x1A104098}{0x00000000}{T2\_TH\_CHANNEL3}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER2 channel 3 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER2 channel 3 threshold configuration bitfield.}
}


\regdoc{0x1A1040C0}{0x00000000}{T3\_CMD}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{11}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\tiny ARM} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~RESET~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~UPDATE~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~STOP~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~START~}}
  \end{bytefield}
}{
  \regitem{Bit 4}{ARM}{R/W}{ADV\_TIMER3 arm command bitfield.}
  \regitem{Bit 3}{RESET}{R/W}{ADV\_TIMER3 reset command bitfield.}
  \regitem{Bit 2}{UPDATE}{R/W}{ADV\_TIMER3 update command bitfield.}
  \regitem{Bit 1}{STOP}{R/W}{ADV\_TIMER3 stop command bitfield.}
  \regitem{Bit 0}{START}{R/W}{ADV\_TIMER3 start command bitfield.}
}


\regdoc{0x1A1040C4}{0x00000000}{T3\_CONFIG}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{8}{\color{lightgray}\rule{\width}{\height}} \bitbox{8}{PRESC} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{3}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~UPDOWNSEL~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~CLKSEL~}} \bitbox{3}{MODE} \bitbox{8}{INSEL}
  \end{bytefield}
}{
  \regitem{Bit 23 - 16}{PRESC}{R/W}{ADV\_TIMER3 prescaler value configuration bitfield.}
  \regitem{Bit 12}{UPDOWNSEL}{R/W}{ADV\_TIMER3 center-aligned mode configuration bitfield:\\- 1'b0: The counter counts up and down alternatively.\\- 1'b1: The counter counts up and resets to 0 when reach threshold.}
  \regitem{Bit 11}{CLKSEL}{R/W}{ADV\_TIMER3 clock source configuration bitfield:\\- 1'b0: FLL\\- 1'b1: reference clock at 32kHz}
  \regitem{Bit 10 - 8}{MODE}{R/W}{ADV\_TIMER3 trigger mode configuration bitfield:\\- 3'h0: trigger event at each clock cycle.\\- 3'h1: trigger event if input source is 0\\- 3'h2: trigger event if input source is 1\\- 3'h3: trigger event on input source rising edge\\- 3'h4: trigger event on input source falling edge\\- 3'h5: trigger event on input source falling or rising edge\\- 3'h6: trigger event on input source rising edge when armed\\- 3'h7: trigger event on input source falling edge when armed}
  \regitem{Bit 7 - 0}{INSEL}{R/W}{ADV\_TIMER3 input source configuration bitfield:\\- 0-31: GPIO[0] to GPIO[31]\\- 32-35: Channel 0 to 3 of ADV\_TIMER0\\- 36-39: Channel 0 to 3 of ADV\_TIMER1\\- 40-43: Channel 0 to 3 of ADV\_TIMER2\\- 44-47: Channel 0 to 3 of ADV\_TIMER3}
}


\regdoc{0x1A1040C8}{0x00000000}{T3\_THRESHOLD}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{TH\_HI} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH\_LO}
  \end{bytefield}
}{
  \regitem{Bit 31 - 16}{TH\_HI}{R/W}{ADV\_TIMER3 threshold high part configuration bitfield. It defines end counter value.}
  \regitem{Bit 15 - 0}{TH\_LO}{R/W}{ADV\_TIMER3 threshold low part configuration bitfield. It defines start counter value.}
}


\regdoc{0x1A1040CC}{0x00000000}{T3\_TH\_CHANNEL0}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER3 channel 0 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER3 channel 0 threshold configuration bitfield.}
}


\regdoc{0x1A1040D0}{0x00000000}{T3\_TH\_CHANNEL1}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER3 channel 1 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER3 channel 1 threshold configuration bitfield.}
}


\regdoc{0x1A1040D4}{0x00000000}{T3\_TH\_CHANNEL2}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER3 channel 2 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER3 channel 2 threshold configuration bitfield.}
}


\regdoc{0x1A1040D8}{0x00000000}{T3\_TH\_CHANNEL3}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{3}{MODE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TH}
  \end{bytefield}
}{
  \regitem{Bit 18 - 16}{MODE}{R/W}{ADV\_TIMER3 channel 3 threshold match action on channel output signal configuration bitfield:\\- 3'h0: set.\\- 3'h1: toggle then next threshold match action is clear.\\- 3'h2: set then next threshold match action is clear.\\- 3'h3: toggle.\\- 3'h4: clear.\\- 3'h5: toggle then next threshold match action is set.\\- 3'h6: clear then next threshold match action is set.}
  \regitem{Bit 15 - 0}{TH}{R/W}{ADV\_TIMER3 channel 3 threshold configuration bitfield.}
}


\regdoc{0x1A104104}{0x00000000}{CG}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{ENA}
  \end{bytefield}
}{
  \regitem{Bit 15 - 0}{ENA}{R/W}{ADV\_TIMER clock gating configuration bitfield. \\- ENA[i]=0: clock gate ADV\_TIMERi.\\- ENA[i]=1: enable ADV\_TIMERi. }
}

